Electrically erasable and programmable memory devices having arrays of memory cells are found in a wide variety of electrical devices. For example, a flash memory cell, also known as a floating gate transistor memory cell, is similar to a field effect transistor, having a source region and a drain region that is spaced apart from the source region to form an intermediate channel region. A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the channel region by a layer of gate oxide. A control gate is fabricated over the floating gate, and it can also be made of doped polysilicon. The control gate is electrically separated from the floating gate by a dielectric layer. Thus, the floating gate is “floating” in the sense that it is insulated from the channel, the control gate and all other components of the flash memory cell.
A flash memory cell is programmed by storing charge on the floating gate. The charge thereafter remains on the gate for an indefinite period even after power has been removed from the flash memory device. Flash memory devices are therefore non-volatile. Charge is stored on the floating gate by applying appropriate voltages to the control gate and the drain or source. For example, negative charge can be placed on the floating gate by grounding the source while applying a sufficiently large positive voltage to the control gate to attract electrons, which tunnel through the gate oxide to the floating gate from the channel region. The voltage applied to the control gate, called a programming voltage, and the duration that the programming voltage is applied as well as the charge originally residing on the floating gate, determine the amount of charge residing on the floating gate after programming.
A flash memory cell can be read by applying a positive control gate to source voltage having a magnitude greater than a threshold voltage. The amount of charge stored on the flash memory cell determines the magnitude of the threshold voltage that must be applied to the control gate to allow the flash memory cell to conduct current between the source and the drain. As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases. During a read operation, a read voltage is applied to the control gate that is large enough to render the cell conductive if insufficient charge is stored on the floating gate, but not large enough to render the cell conductive if sufficient charge is stored on the floating gate. During the read operation, the drain, which is used as the output terminal of the cell, is precharged to a positive voltage, and the source is coupled to ground. Therefore, if the floating gate of the flash memory cell is sufficiently charged, the drain will remain at the positive voltage. If the floating gate of the flash memory cell is not sufficiently charged, the cell will ground the drain.
Before a flash memory cell can be programmed, it must be erased by removing charge from the floating gate. The cell can be erased by applying a gate-to-source voltage to the cell that has a polarity opposite that used for programming. Specifically, the control gate is grounded, and a large positive voltage is applied to the source to cause the electrons to tunnel through the gate oxide and deplete charge from the floating gate. In another approach, a relatively large negative voltage is applied to the control gate, and a positive voltage, such as a supply voltage, is applied to the source region. As part of the erase process, the flash memory cells undergo an erase verify process. An erase verify process is essentially the same as a normal read procedure.
A typical flash memory device includes a memory array containing a large number of flash memory cells arranged in rows and columns. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic flash memory cell configuration for each is arranged. FIG. 1 illustrates a typical NAND flash memory array 10 of conventional design. The array 10 is comprised of a large number of flash memory cells, collectively indicated by reference numeral 14. The array of flash memory cells 14 is typically divided into a number of blocks, one of which is shown in FIG. 1. Each block includes a number of rows, which, in the example shown in FIG. 1, includes 32 rows. The cells 14 in the same row have their control gates coupled to a common word select line 30, each of which receives a respective word line signal WL0-WL31. The cells 14 in the same column have their sources and drains connected to each other in series. Thus all of the memory cells 14 in the same column of each block are typically connected in series with each other. The drain of the upper flash memory cell 14 in the block is coupled to a bit line 20 through a first select gate transistor 24. The conductive state of the transistors 24 in each block are controlled by a source gate SG(D) signal. Each of the bit lines 20 output a respective bit line signal BL1-BLN indicative of the data bit stored in the respective column of the array 10. The bit lines 20 extend through multiple blocks to respective sense amplifiers (not shown). The source of the lower flash memory cell 14 in the block is coupled to a source line 26 through a second select gate transistor 28. The conductive state of the transistors 28 in each block are controlled by a source gate SG(S) signal. The source line 26 receives a signal SL having various magnitudes depending upon whether the memory cells 14 are being programmed, read or erased.
A read operation is performed on a row-by-row basis. When a read operation is to be performed for a selected block, the source line 26 is coupled to ground, and the select gate transistors 24, 28 for that block are turned ON responsive to high SG(D) and SG(S) signals. Also, the bit line 20 for each column is precharged to the supply voltage VCC. Finally, a read voltage is applied to a word select line 30 for the selected row, thereby applying the read voltage to the control gates of all of the flash memory cells 14 in that row. As explained above, the magnitude of the read voltage is sufficient to turn ON all flash memory cells 14 that do not have a sufficiently charged floating gate, but insufficient to turn ON all cells that have a sufficiently charged floating gate. A voltage having a higher magnitude is applied to the word select lines 30 for all of the non-selected rows. This voltage is large enough to turn ON the flash memory cells 14 even if their floating gates are storing insufficient charge to be read as programmed. As a result, the bit line 20 for each column will be low if the cell 14 in that column of the selected row is not storing enough charge to turn OFF the device at that gate bias. Otherwise the bit line 20 remains high at VCC. The voltage on each bit line 20 is compared to a reference voltage by a respective sense amplifier (not shown). If the voltage on the bit line 20 is less than the reference voltage, the sense amplifier outputs a voltage corresponding to a “1” binary value of the read data bit. If the voltage on the bit line 20 is greater than the reference voltage, the sense amplifier outputs a voltage corresponding to a “0” binary value of the read data bit.
When a selected row of flash memory cells 14 are to be erased, the word select line 30 for the selected row is coupled to ground, and the bit lines BL1,2 . . . N for each column is coupled to a large positive voltage. A high SG(D) signal then turns ON the select gate transistors 24 to apply the positive voltage to the drains of the flash memory cells 14. The positive voltage then depletes charge from the floating gates in all of the cells 14, thereby erasing all of the memory cells 14 in the selected row. The flash memory cells 14 are normally erased on a block-by-block basis by grounding the word select lines 30 for all of the cells 14 in the block. Insofar as erasing the cells 14 by depleting charge from their floating gates, erasing the cells 14 effectively programs them to store logic “1” bit values.
When a selected row of cells 14 are to be programmed, a programming voltage is applied to the word select line 30 for the selected row, and a voltage sufficient to turn ON the remaining cells 14 is applied to the control gates of the remaining flash memory cells 14. Also, the first column select transistors 24 are turned ON and voltages corresponding to the data bits that are to be programmed are applied to the respective bit lines. If the voltage of a bit line 20 is at ground corresponding to a logic “0,” additional charge will be stored in the floating gate of the flash memory cell 14 in that column of the selected row. Otherwise, a voltage on the bit line 20 corresponding to a logic “1” prevents any additional charge from being stored on the floating gate. Programming is therefore performed on a row-by-row basis.
Conventional flash memory devices generally contain a large number of memory cells 14 in each block. For example, a flash memory device block having 32 rows and 1024 columns of memory cells 14 in each block contains over 32,000 memory cells 14. Since flash memory cells 14 are erased on a block-by block basis, erasing the memory cells 14 in a block entails removing charge from over 32,000 memory cells. Programming the memory cells 14 can also require the transfer of a considerable amount of charge to the memory cells 14. Using the same example of a flash memory device having 1024 columns of memory cells 14, programming a row of memory cells 14 requires simultaneously applying charge to 1024 memory cells 14 since flash memory cells 14 are programmed on a row-by-row basis. As a result, the peak current consumed by a flash memory device during erase and/or programming can be considerable. The peak current consumption during the erase verify process can also be excessive, and can further result in a large amount of power being consumed over a considerable period. The problem of excessive power being consumed by flash memory devices can even be more serious in high data capacity applications where several flash memory devices are used in parallel and may be erased and/or programmed together.
Manufacturers of flash memory devices have taken steps to alleviate the problem of excessive peak power consumption. One conventional approach is to delay the rate at which current is applied to the memory cells 14 while they are being erased and/or programmed. This approach reduces the speed at which flash memory devices can be erased and programmed, but many users prefer limited peak power consumption over increased operating speed. An example of a conventional approach for delaying the rate at which current is applied to flash memory cells to limit peak power consumption is shown in FIG. 2. A power limiting circuit 40 includes an NMOS transistor 42 that has its drain coupled to a large positive voltage VCC. The source of the transistor 42 is coupled to one of the bit lines (“BL”) 20 (FIG. 1), and the gate of the transistor is coupled to a control circuit 46. The bit line 20 is also connected to the select gate transistor 24 (FIG. 1) in each of the respective blocks. Although only one transistor 42 connected to one bit line 20 is shown in FIG. 2, it will be understood that a respective transistor 42 is provided for each column, and its source is connected to the bit line 20 for that column.
The control circuit 46 includes an inverter 50 coupled through a resistor 52 to the gate of the transistor 42. The inverter 50 is powered by a voltage HV having a magnitude that is greater than that of the voltage VCC by at least the threshold voltage of the transistor 42. As a result, when the output of the inverter 50 is high responsive to an active low ERASE* signal, the transistor 42 can couple the full magnitude of VCC to the bit line BL. A capacitor 56 coupled to either ground or a negative supply voltage VSS causes the output of the inverter 50 to be low-pass filtered. As a result, when the output of the inverter 50 transitions high responsive to the low ERASE* signal, the gate of the transistor 42 transitions high relatively slowly with a time constant corresponding to the product of the resistance of the resistor 52 and the capacitance of the capacitor 56. As a result, the peak current applied to the bit line BL is relatively low. Insofar as some users prefer faster programming time over reduced peak power consumption, the ERASE* signals may be coupled to the inverter 50 through a fuse or anti-fuse 58 to allow a user to select either the reduced peak power consumption mode or the fast programming mode.
Although not shown in FIG. 2, control circuits in a flash memory device using the power limiting circuit 40 increase the erase and/or programming times when the user selects the reduced peak power consumption mode to allow sufficient charge to be coupled to or from the floating gates of the memory cells 14.
The power limiting circuit 40 shown in FIG. 2 is adequate in many circumstances. However, the circuit 40 does not provide good control over the magnitude of the peak power drawn by the bit lines BL. As shown in FIG. 3, the bit line current provided by the power limiting circuit 40 is not very constant, and has a peak value that is difficult to control. In particular, changes in temperature or process variations can allow the peak power consumed to vary significantly. Therefore, the conventional power limiting circuit 40 can sometimes allow excessive power to be consumed.
There is, therefore, a need for a flash memory device that can be selectively enabled and that provides better control over the peak power consumed by memory cells during programming and/or erase, including during erase verification.